A logic ‘0’ on the ENABLE input enables the clock generator and its output frequency is defined by: 1.4 P1C1 The output signal from the clock generator is connected to the clock inputs of the two D-type flip-flops IC1.A and IC1.B. These two flip flops are connected together in a ring to form a 2-bit shift register so that the Q output of IC1.B is fed back to the D input of IC1.A and the Q output of IC1.A is fed into the D input of IC1.B. This configuration supplies the 4 phase impulses necessary to provide motor rotation. When the DIRECTION input is changed to logic zero IC2C and IC2D operate as non-inverting gates, reversing the phase sequence of the output signals and making the motor spin in the opposite direction.
The actual rotation direction will depend on the sense of the motor windings. Swapping the outer two coil connections on one of the windings will reverse the direction if this is necessary. With the components specified the circuit oscillates at a frequency of 10 Hz. The clock frequency can be adjusted between 0.2 and 100 Hz by substituting different values for P1 and C1. It is important to ensure that power drawn by the stepper motor is within the power handling capability of the driver transistors T1 to T4. Diodes D1 to D4 are necessary to conduct away the back-EMF produced each time a drive impulse to each of the motor coils is switched off.